三维扫描仪中图像处理专用集成电路设计 二

文档字数:17785,页数:41 

三维扫描仪中图像处理专用集成电路设计
摘    要
三维彩色信息获取系统目的是获取对象的三维空间坐标和颜色信息。它是计算机视觉研究的重要内容，也是当前信息科学研究中的一个重要热点。三维信息技术在机械加工、影视特技制作、虚拟现实等行业有广泛的应用前景。针对原三维激光彩色扫描仪3DLCS 存在的问题,现采用主从式系统结构、并行处理技术、快速算法和基于FPGA 设计的专用集成电路，研制了新的实时可重构三维激光彩色信息获取系统。该扫描仪由基于FPGA 处理器的从机完成重要的图像处理快速算法。对三维重建有用信息经计算机接口送入主机，在主机上进行三维重建和三维构型。实时三维信息获取系统大大提高了获取物体三维信息的速度，可以实时地在计算机上处理和显示获得的立体三维图形。新的设计不但显著地改进了系统的整体性能，而且降低了产品成本。此外，提高了保密性，可实现特定功能和应用于特殊的领域。
研制了具有完全自主知识产权的实时三维扫描仪视频图像处理专用集成电路。该集成电路是实现系统快速算法的核心，使用现场可编程器FPGA 器件EP1K50 实现提取激光线、提取人头轮廓线和提取中心颜色线算法；该集成电路还要实现系统所需的控制逻辑。控制部分包括将视频采集输出端口信号转化为RGB 真彩色信号的数据锁存模块、各FIFO 缓存器的输入输出控制模块和系统需要的其它信号控制模块。提出提取轮廓线快速算法，即由FPGA 处理器与主机交互式共同快速完成提取人头正侧影轮廓线算法。该专用集成电路研制是整个系统的关键。
乘法器是现代电子设计、信号处理中的一个重要的部件。我们设计并行高速乘法器的目的是为实时三维扫描仪的图像处理专用集成电路提供一个高速的运算单元。总结了常用的乘法器设计方法。再重点研究了一个基于华莱士树结构的15位并行高速乘法器设计与实现。在一块FPGA 芯片上完成其功能。并行高速乘法器的设计与实现使得在芯片内部完成高精度的矩阵计算变成现实。高速乘法器研制为三维扫描仪将来做成片上集成系统(SOC)打下基础。

关键词： 三维信息获取  现场可编程门阵列  快速算法  专用集成电路  乘法器设计

The Design of ASIC for Image Processing of 3D Color Scanner
Abstract
The 3D color information acquisition system can obtain the coordinate and color information of the object surface in the 3D space. It is important for computer vision and one of the research focuses in information technology and it is widely applied in areas such as industry manufacture, film, TV and virtual reality, etc. The new real time reconfigurable 3D laser colour information acquisition system adopting master-slave system architecture using parallel processing technology，fast algorithms and ASIC which made by FPGA has been developed to overcome the problems of the former 3D laser color scanner (3DLCS). It can accomplish important image processing fast algorithms by slave system based on FPGA. Then the important information is sent into host computer through PCI interface to accomplish advanced image processing, 3D reconstruction and 3D modeling. The new 3D information acquisition system can acquire 3D and colour information of object in real time and the 3D images are displayed promptly on the screen of host computer. The system performance is improved greatly and the devices are low cost. In addition, it has good security and can implement special function and is applicable to many special cases. A patent is applying for the real time reconfigurable 3D scanner.
Multipliers are one of the important components in digital signal processing. It is applied to the chip of digital signal processing, especially digital image processing. The parallel multiplier designed by us is used as a high-speed unit for the image processing ASIC of real time 3D scanner. The usual design methods of multiplier are summarized. A 15 bit parallel high-speed multiplier based on Wallace tree is implemented in EP1K50 so that high accurate matrix computing can be accomplished in a chip for 3D scanner. High-speed multiplier is very important for the development of the real time reconfigurable 3DLCS, especially to make 3D scanner into SOC in the future.
A video image-processing special integrate circuit for the real time 3D scanner is developed, which possess of independence knowledge property right by us. The ASIC is the system core for implementation of the key fast algorithms. The algorithms of extracting central line of laser stripe, head contour and central colour line from video image are accomplished by FPGA processor, which is made of EPEK50. In addition, the ASIC must do control function that includes data lock module, I/O control module for FIFO and other signal control modules that is required by system. The data lock module can translate the video capture port signal into true colour RGB signal. An interactive fast algorithm of extracting the head contour has been proposed for real-time image processing, which is accomplished by FPGA processor and host computer together. The development of ASIC is the most important to the whole system.
Key words：3D information acquisition  FPGA  fast algorithm  ASIC  Multiplier design

目    录
摘    要I
AbstractII
目    录III
绪    论1
第 一 章  轮廓线的提取2
1.1  引言2 
1.2  算法实现3

第 二 章  高速乘法器设计6
2.1  引言6  
2.2  布思算法(Booth Algorithm) 7
2.2.1  无符号数一位乘法7
2.2.2  符号数一位乘法9
2.2.3  布思算法(Booth Algorithm) 10
2.2.4  高基布思算法(Hig Radix Booth Algorithm) 11
2.2.5非重叠三位编码13
2.3  华莱士树(Wallace Tree) 15
2.3.1  保留进位加法器15
2.3.2  华莱士树(Wallace Tree) 16
2.4  超前进位加法器19
2.4.1  半加器和全加器19
2.4.2  超前进位加法器20
2.5  VHDL硬件实现21

第 三 章  ACEX1K50器件特性22
3.1引言22
3.2  隐埋阵列块(EAB) 23
3.3  逻辑阵列块(LAB)和逻辑单元(LE) 24
3.4快速互连通道和I/O单元25
3.5其他特点25
参考文献27
总    结28

附    录29

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